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  to learn more about on semiconductor, please visit our website at www.onsemi.com please note: as part of the fairchild semiconductor integration, some of the fairchild orderable part numbers will need to change in order to meet on semiconductors system requirements. since the on semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the fairchild part numbers will be changed to a dash (-). this document may contain device numbers with an underscore (_). please check the on semiconductor website to verify the updated device numbers. the most current and up-to-date ordering information can be found at www.onsemi.com . please email any questions regarding the system integration to fairchild_questions@onsemi.com . is now part of on semiconductor and the on semiconductor logo are trademarks of semico nductor components industries, llc dba on semiconductor or its subsid iaries in the united states and/or other countries. on semiconductor ow ns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellec tual property. a listing of on semiconductor?s product/patent cover age may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semicon ductor makes no warranty, representation or guarantee regarding the s uitability of its products for any particular purpose, nor does on semico nductor assume any liability arising out of the application or use of any product or circuit, and speci?ca lly disclaims any and all liability, including without limitation spe cial, consequential or incidental damages. buyer is responsible for i ts products and applications using on semiconductor products, including compliance with all laws, regul ations and safety requirements or standards, regardless of any suppor t or applications information provided by on semiconductor. ?typica l? parameters which may be provided in on semiconductor data sheets and/or speci?cations can and do vary in diffe rent applications and actual performance may vary over time. all operat ing parameters, including ?typicals? must be validated for each custo mer application by customer?s technical experts. on semiconductor does not convey any license und er its patent rights nor the rights of others. on semiconductor products a re not designed, intended, or authorized for use as a critical compone nt in life support systems or any fda class 3 medical devices or medical devices with a same or similar classi?ca tion in a foreign jurisdiction or any devices intended for implantation i n the human body. should buyer purchase or use on semiconductor products fo r any such unintended or unauthorized application, buyer shall indemnify and hold on semico nductor and its of?cers, employees, subsidiaries, af?liates, and di stributors harmless against all claims, costs, damages, and expense s, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associa ted with such unintended or unauthorized use, even if such claim alleges th at on semiconductor was negligent regarding the design or manufacture o f the part. on semiconductor is an equal opportunity/af?rmative action employer. this literatu re is subject to all applicable copyright laws and is not for resale in any manne r.
74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs ?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 rev. 1.6.1 74lcx32 features 5v tolerant inputs 2.3vC3.6v v cc specifications provided 5.5ns t pd max. (v cc = 3.3v), 10 a i cc max. power down high impedance inputs and outputs 24ma output drive (v cc = 3.0v) latch-up performance exceeds jedec 78 conditions esd performance:C human body model > 2000v C machine model > 150v leadless dqfn package general description the lcx32 contains four 2-input or gates. the inputstolerate voltages up to 7v allowing the interface of 5v systems to 3v systems. the 74lcx32 is fabricated with advanced cmos tech- nology to achieve high speed operation while maintain- ing cmos low power dissipation. ordering information note: 1. dqfn package available in tape and reel only. device also available in tape and reel. specify by appending suffix letter x to the ordering number. all packages are lead free per jedec: j-std-020b standard. order number package number package description 74lcx32m m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74lcx32sj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74LC32BQX (1) mlp14a 14-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 3.0mm 74lcx32mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide implements proprietary noise/emi reduction circuitry low voltage quad 2-input or gate with 5v tolerant inputs december 2013
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 rev. 1.6.1 2 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs connection diagrams pin assignments for soic, sop, and tssop pad assignments for dqfn (top view) pin description logic symbol ieee/iec pin names description a n , b n inputs o n outputs (bottom view) dap no connect note: dap (die attach pad)
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 2. i o absolute maximum rating must be observed. recommended operating conditions (3) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 3. unused inputs must be held high or low. they may not float. symbol parameter rating v cc supply voltage C0.5v to +7.0v v i dc input voltage C0.5v to +7.0v v o dc output voltage, output in high or low state (2) C0.5v to v cc + 0.5v i ik dc input diode current, v i < gnd C50ma i ok dc output diode current v o < gnd C50ma v o > v cc +50ma i o dc output source/sink current 50ma i cc dc supply current per supply pin 100ma i gnd dc ground current per ground pin 100ma t stg storage temperature C65c to +150c symbol parameter min. max. units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 0 5.5 v v o output voltage, high or low state 0 v cc v i oh / i ol output current v cc = 3.0vC3.6v 24 ma v cc = 2.7vC3.0v 12 v cc = 2.3vC2.7v 8 t a free-air operating temperature C40 85 c ? t / ? v input edge rate, v in = 0.8vC2.0v, v cc = 3.0v 0 10 ns / v 74lcx32 rev. 1.6.1 3
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs dc electrical characteristicsac electrical characteristics note: 4. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). symbol parameter v cc (v) conditions t a = C40c to +85c units min. max. v ih high level input voltage 2.3C2.7 1.7 v 2.7C3.6 2.0 v il low level input voltage 2.3C2.7 0.7 v 2.7C3.6 0.8 v oh high level output voltage 2.3C3.6 i oh = C100a v cc C 0.2 v 2.3 i oh = C8ma 1.8 2.7 i oh = C12ma 2.2 3.0 i oh = C18ma 2.4 i oh = C24ma 2.2 v ol low level output voltage 2.3C3.6 i ol = 100a 0.2 v 2.3 i ol = 8ma 0.6 2.7 i ol = 12ma 0.4 3.0 i ol = 16ma 0.4 i ol = 24ma 0.55 i i input leakage current 2.3C3.6 0 v i 5.5v 5.0 a i off pow er-off leakage current 0 v i or v o = 5.5v 10 a i cc quiescent supply current 2.3C3.6 v i = v cc or gnd 10 a 3.6v v i 5.5v 10 ? i cc increase in i cc per input 2.3C3.6 v ih = v cc C 0.6v 500 a symbol parameter t a = C40c to +85c, r l = 500 ? units v cc = 3.3v 0.3v, c l = 50pf v cc = 2.7v, c l = 50pf v cc = 2.5v 0.2v, c l = 30pf min. max. min. max. min. max. t phl , t plh propagation delay 1.5 5.5 1.5 6.2 1.5 6.6 ns t oshl , t oslh output to output skew (4) 1.0 ns 74lcx32 rev. 1.6.1 4
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs dynamic switching characteristicscapacitance symbol parameter v cc (v) conditions t a = 25c unit typical v olp quiet output dynamic peak v ol 3.3 c l = 50pf, v ih = 3.3v, v il = 0v 0.8 v 2.5 c l = 30pf, v ih = 2.5v, v il = 0v 0.6 v olv quiet output dynamic valley v ol 3.3 c l = 50pf, v ih = 3.3v, v il = 0v C0.8 v 2.5 c l = 30pf, v ih = 2.5v, v il = 0v C0.6 symbol parameter conditions typical units c in input capacitance v cc = open, v i = 0v or v cc 7p f c out output capacitance v cc = 3.3v, v i = 0v or v cc 8p f c pd pow er dissipation capacitance v cc = 3.3v, v i = 0v or v cc , f = 10mhz 25 pf 74lcx32 rev. 1.6.1 5
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs ac loading and waveforms (generic for lcx family) figure 1. ac test circuit (c l includes probe and jig capacitance) waveform for inverting and non-inverting functions propagation delay. pulse width and t rec waveforms 3-state output high enable and disable times for logic 3-state output low enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall figure 2. waveforms (input characteristics; f = 1mhz, t r = t f = 3ns) test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v v cc x 2 at v cc = 2.5 0.2v t pzh , t phz gnd symbol v cc 3.3v 0.3v 2.7v 2.5v 0.2v v mi 1.5v 1.5v v cc / 2 v mo 1.5v 1.5v v cc / 2 v x v ol + 0.3v v ol + 0.3v v ol + 0.15v v y v oh C 0.3v v oh C 0.3v v oh C 0.15v 74lcx32 rev. 1.6.1 6
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs schematic diagram (generic for lcx family) 74lcx32 rev. 1.6.1 7
?1995 fairchild semiconductor corporation www.fairchildsemi.com 74lcx32 low voltage quad 2-input or gate with 5v tolerant inputs tape and reel specification tape format for dqfn tape dimensions inches (millimeters) reel dimensions inches (millimeters) pa ck ag e designator tape section number of cavities cavity status cover tape status bqx leader (start end) 125 (typ.) empty sealed carrier 3000 filled sealed tr ailer (hub end) 75 (typ.) empty sealed tape size a b c d n w1 w2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) 74lcx32 rev. 1.6.1 8
front view top view ? all lead tips notes: a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters. c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions d. dimensioning and tolerances per ansi y14.5m, 2009. e. landpattern standard: sop65p640x110-14m.f. drawing file name: mkt-mtc14rev7. 0.43typ 0.2 c b a 8 1 7 14 a b ? 3.2 6.4 pin#1 ident 1.2 max 0.1 c all lead tips c 0.65 0.300.19 0.13 a b c ? 0.90 +0.15 -0.10 0.200.09 see detail a ?723 %27720 gage plane 0.25 seating plane 0.09 min 0.09 min ? 1.00 detail a ?? recommended land pattern 6.10 0.65 1.65 0.45

1.70 5.60 1.27 0.65 1.501.25 1.75 max 0.250.10 c 4.003.80 8.758.50 6.00 (0.33) 0.510.35 7.62 1.27 1 pin #1 ident. a b 0.250.19 a 0.500.25 x 45 r0.10 r0.10 (1.04) 0.36 80 0.900.50 detail a scale 16 : 1 gage plane seating plane top view front view side view 14 7 8 1 7 8 land pattern recommendation notes: a. conforms to jedec ms-012, variation ab, issue c b. all dimensions are in millimeters c. dimensions do not include mold flash or burrs d. land pattern standard: soic127p600x145-14m e. conforms to asme y14.5m, 2009 d. drawing filename: mkt-m14arev14 14 0.10 c 0.25 m c b a
b. dimensions are in millimeters. a. conforms to jedec registration mo-241, variation aa top view bottom view recommended land pattern a b side view pin #1 ident 3.00 2.50 0.50 0.50 2.00 1.00 max 1.70 max 3.50 max 1.40 max 2.20 max 4.00 max 0.50 typ 0.24 typ (0.90) 0.50 typ 0.05 c 2x 0.05 c 2x 0.08 c 0.10 c seating plane c ? 0.10 c a b 0.05 c pin #1 quadrant c. dimensions and tolerances per asme y14.5m, 2009. d. land pattern recommendation is existing industry land pattern. e. drawing filename: mkt-mlp14arev2. (14x) (14x) ? ? ? ? ? ? ? ?
www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including typic als must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your localsales representative ? semiconductor components industries, llc


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